Onchip Interconnect Exploration for Multicore Processors Utilizing FPGAs

Dual core microprocessors are currently available and higher processor-count architectures will dominate the multicore market. A complex part of these higher order multicore designs will be the interconnection scheme that exists onchip and how exactly that interconnection is best used and configured. While FPGAs currently support a variety of onchip bus interconnects, there is a gap in the tools to provide Network on Chip (NoC) exploration. A Network on Chip is a onchip packet switched network that is used for computational elements (typically standard processors) to communicate with each other. In this paper, we present our NoC emulation tool (NoCem) and provide an example memory architecture exploration platform that can be created.